The present invention relates to semiconductor fabricating technology, and more particularly, to a nonvolatile memory cell including a dual gate using a phase-change material for a channel, a nonvolatile memory device and a method for driving the same.
In general, semiconductor memory devices may be classified into volatile memory devices such as a dynamic random access memory (DRAM) device and a static random access memory (SRAM) device and nonvolatile memory devices such as a flash memory device and an electrically erasable programmable read-only memory (EEPROM) device according to whether or not the memory device maintains data stored in memory cells even when power to the device is turned off.
Among the nonvolatile memory devices, the flash memory device is being widely used in electronic instruments such as a digital camera, a cellular phone and an MPEG audio layer-3 (MP-3). However, the flash memory device requires a large amount of time when writing data or reading out stored data. Therefore, instead of the flash memory device, there have been developed new semiconductor devices such as a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device and a phase-change random access memory (PRAM) device.
The PRAM device, which is referred to as a phase-change memory device hereinafter, has an amorphous state or a polycrystalline state according to phase transition of a chalcogenide compound constructing its phase-change layer and stores data using the difference between resistances of the above two states. That is, the phase-change memory device stores data with a logic value ‘0’ or ‘1’ using reversible phase-change of a phase-change layer formed of germanium-antimony-tellurium (Ge—Sb—Te, GST) that is the chalcogenide compound according to amplitude and length of a pulse supplied thereto. For instance, if a reset pulse (reset current) is supplied thereto, the phase-change layer melts away and thus becomes a high resistance state of the amorphous state, i.e., a reset state ‘1’. Meanwhile, if a set pulse (set current) is supplied thereto, the phase-change layer becomes a low resistance state of the polycrystalline state, i.e., a set state ‘0’.
FIG. 1 illustrates a cross-sectional view of a conventional phase-change memory device.
Referring to FIG. 1, a transistor including a gate electrode 14 and source and drain regions 16-1 and 16-2 is formed in a substrate 10 including an isolation layer 11. Furthermore, a first inter-layer insulation layer 17 is formed on the substrate 10 and first via contacts 18 respectively connected to the source and drain regions 16-1 and 16-2 are formed in the first inter-layer insulation layer 17. Herein, the gate electrode 14 of the transistor acts as a word line of the phase-change memory device.
First metal lines 19 respectively connected to the first via contacts 18 are formed on the first inter-layer insulation layer 17. Moreover, a second inter-layer insulation layer 20 is formed on the first inter-layer insulation layer 17. A second via contact 21 connected to the first metal line 19 is formed in the second inter-layer insulation layer 20. A phase-change layer 22 connected to the second via contact 21 is formed on the second inter-layer insulation layer 20.
A third inter-layer insulation layer 23 is formed on the second inter-layer insulation layer 20 to cover the phase-change layer 22. A third via contact 24 connected to the phase-change layer 22 is formed in the third inter-layer insulation layer 23. A second metal line 25 connected to the third via contact 24 is formed on the third inter-layer insulation layer 23. Herein, the second metal line 25 acts as a bit line of the phase-change memory device.
For illustration purposes, a reference numeral ‘12’ represents a gate insulation layer; a reference numeral ‘13’ indicates a gate conductive layer; and a reference numeral ‘15’ presents a spacer formed on a sidewall of the gate electrode 14, wherein the gate electrode 14 includes the gate insulation layer 12 and the gate conductive layer 13 that are vertically stacked.
In the conventional phase-change memory device described above, a unit cell includes the transistor, i.e., a cell transistor, and the phase-change layer 22. Accordingly, in each of unit cells, at least one first via contact 18 is required to connect the drain region 16-2 and ground (GND). As a result, the size of the unit cell increases. Meanwhile, the phase transition of the phase-change layer 22 is caused by heat from conducting electricity provided from the second via contact 21 that is a lower electrode. Thus, a large amount of a reset current is required to induce the phase transition of the phase-change layer 22, which increases the channel width of the cell transistor, so that it is difficult to implement a high density memory cell array.